US 12,292,831 B2
Enhanced data reliability in multi-level memory cells
Deping He, Boise, ID (US); and David Aaron Palmer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 26, 2024, as Appl. No. 18/616,993.
Application 18/616,993 is a continuation of application No. 16/999,985, filed on Aug. 21, 2020, granted, now 11,960,398.
Prior Publication US 2024/0320153 A1, Sep. 26, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 11/10 (2006.01); G06F 11/30 (2006.01); G06F 12/0811 (2016.01); G06F 12/0882 (2016.01); G06F 12/0891 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 11/1068 (2013.01); G06F 11/3037 (2013.01); G06F 12/0882 (2013.01); G06F 12/0891 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for wireless communication, comprising:
a data generator;
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the apparatus to:
identify that a first set of data is configured to cause each memory cell of one or more memory cells associated with the first set of data to store a second quantity of bits that is less than a first quantity of bits in response to operating in a first mode associated with increased reliability relative to a second mode, wherein the one or more memory cells are capable of storing the first quantity of bits;
generate, via the data generator, a second set of data for storing with the first set of data in the one or more memory cells in response to identifying that the first set of data is configured to cause each memory cell to store the second quantity of bits and operating in the first mode, wherein the second set of data comprises redundant data associated with the first set of data; and
transmit, to the one or more memory devices, a write command that comprises an indication for the one or more memory devices to store the first set of data and the second set of data in the one or more memory cells, wherein one or more bits from the first set of data and at least one bit from the second set of data are stored in each memory cell of the one or more memory cells.