US 12,292,798 B2
Apparatuses, systems, and methods for module level error correction
Sujeet Ayyapureddi, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/822,915.
Prior Publication US 2024/0070025 A1, Feb. 29, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1096 (2013.01) 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory devices each configured to provide a respective one of a plurality of codewords as part of a read operation, wherein each of the plurality of codewords includes a respective plurality of data bits and a respective plurality of parity bits; and
an error correction code (ECC) circuit configured to detect errors in a first set of data bits and a first set of parity bits based on the first set of data bits and the first set of parity bits, wherein the first set of data bits includes a first portion of data bits in the respective plurality of data bits of each of the plurality of codewords and the first set of parity bits includes a first portion of parity bits in the respective plurality of parity bits of each of the plurality of codewords.