CPC G06F 11/108 (2013.01) [G06F 11/1096 (2013.01); G06F 12/02 (2013.01)] | 20 Claims |
1. A data storage device comprising:
a plurality of memory dies; and
a processor coupled with the plurality of memory dies and configured to:
store data and parity information for the data in locations in the plurality of memory dies;
determine that at least one location in the plurality of memory dies has a lower performance than the locations storing the parity information; and
move the parity information to the at least one location in the plurality of memory dies that has the lower performance.
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