US 12,292,793 B2
Memory device, memory system, and method of operating the same
Jong-Wook Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 19, 2023, as Appl. No. 18/355,157.
Application 18/355,157 is a continuation of application No. 17/587,418, filed on Jan. 28, 2022, granted, now 11,740,967.
Application 17/587,418 is a continuation of application No. 17/306,345, filed on May 3, 2021, granted, now 11,269,724, issued on Mar. 8, 2022.
Application 17/306,345 is a continuation of application No. 16/666,617, filed on Oct. 29, 2019, granted, now 10,997,020, issued on May 4, 2021.
Application 16/666,617 is a continuation of application No. 15/154,277, filed on May 13, 2016, granted, now 10,545,820, issued on Jan. 28, 2020.
Application 15/154,277 is a continuation of application No. 13/861,676, filed on Apr. 12, 2013, granted, now 9,350,386, issued on May 24, 2016.
Claims priority of provisional application 61/623,221, filed on Apr. 12, 2012.
Claims priority of application No. 10-2013-0028241 (KR), filed on Mar. 15, 2013.
Prior Publication US 2023/0359524 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/52 (2006.01); G06F 11/10 (2006.01); H03M 13/05 (2006.01); H03M 13/09 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1048 (2013.01); G11C 29/52 (2013.01); H03M 13/05 (2013.01); H03M 13/09 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array including a plurality of memory cells;
a write command circuit configured to receive a read-modify-write (RMW) command;
a first pin configured to receive write data;
a second pin configured to receive a data masking signal;
a data modulation circuit configured to:
read first data from the memory cell array;
receive the write data through the first pin and the data masking signal through the second pin; and
generate modulation data by replacing a portion of the first data from the memory cell array with a first portion of the write data; and
an error correction code (ECC) circuit configured to generate first parity data based on the modulation data, and store a codeword including the modulation data and the first parity data, in the memory cell array.