US 12,292,792 B1
Erasure coding techniques for flash memory
Robert Lercari, Thousand Oaks, CA (US); Craig Robertson, Simi Valley, CA (US); and Mike Jadon, Manhattan Beach, CA (US)
Assigned to Radian Memory Systems, LLC, Plano, TX (US)
Filed by Radian Memory Systems, LLC, Plano, TX (US)
Filed on May 19, 2023, as Appl. No. 18/199,456.
Application 18/199,456 is a continuation of application No. 17/498,629, filed on Oct. 11, 2021, abandoned.
Application 17/498,629 is a continuation of application No. 16/707,934, filed on Dec. 9, 2019, granted, now 11,175,984, issued on Nov. 16, 2021.
Int. Cl. G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 9/30029 (2013.01); G06F 11/0772 (2013.01); G06F 11/0784 (2013.01); G06F 11/3037 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A storage system comprising:
a host system, having at least one processor; and
one or more storage drives;
wherein:
a given one of the storage drives comprises a memory controller, channels, and, on each of the channels, flash memory dies;
the host system is configured to send a discovery command to the memory controller, and the memory controller is configured to responsively report, to the host system, a number of the channels and a number of the flash memory dies;
the host system is configured to use the reported number of channels and the reported number of flash memory dies to select a number of the channels that are to be associated with a virtual memory unit, and a number of the flash memory dies that are to be associated with the virtual unit, and to send the host-selected numbers to the given one of the storage drives;
the host system is configured to send write requests addressed to the virtual storage unit, with write data;
the memory controller is configured to service each of the write requests by identifying a subset of the flash memory dies which correspond to the host-selected numbers, and by issuing commands to the subset of the flash memory dies to store the write data; and
the memory controller is configured to calculate error correction information for the write data according to a computation formula that varies according to at least one of the host-selected numbers.