US 12,292,791 B2
Systems and methods for isolating an accelerated function unit and/or an accelerated function context
Sundar Nadathur, Cupertino, CA (US); Pratik M. Marolia, Hillsboro, OR (US); Henry M. Mitchel, Wayne, NJ (US); Joseph J. Grecco, Saddle Brook, NJ (US); Utkarsh Y. Kakaiya, Folsom, CA (US); and David A Munday, Santa Cruz, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 30, 2024, as Appl. No. 18/622,897.
Application 18/622,897 is a continuation of application No. 17/723,383, filed on Apr. 18, 2022, granted, now 11,966,281.
Application 17/723,383 is a continuation of application No. 15/940,779, filed on Mar. 29, 2018, granted, now 11,307,925, issued on Apr. 19, 2022.
Prior Publication US 2024/0248792 A1, Jul. 25, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/0793 (2013.01) [G06F 11/0706 (2013.01); G06F 11/0721 (2013.01); G06F 11/0751 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a user partition of programmable logic circuitry reconfigurable during runtime with a user-defined accelerator; and
a static partition of programmable logic circuitry not to be reconfigured during runtime, wherein the static partition is to isolate the user-defined accelerator in response to identifying a protocol violation in a communication of the user-defined accelerator.