US 12,292,786 B1
Server interrupt operation execution method and apparatus, device and storage medium
Shuaihao Zhang, Jiangsu (CN)
Assigned to SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Suzhou (CN)
Filed by SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Filed on Dec. 25, 2024, as Appl. No. 19/001,546.
Application 19/001,546 is a continuation of application No. PCT/CN2023/102843, filed on Jun. 27, 2023.
Claims priority of application No. 202211483037.5 (CN), filed on Nov. 24, 2022.
Int. Cl. G06F 1/30 (2006.01); G06F 1/324 (2019.01); G06F 11/07 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 1/30 (2013.01); G06F 1/324 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A server interrupt operation execution method, wherein the server is used to execute power failure operation, and the server comprises a first component which does not participate in the power failure operation and is a transient power reduction component, a second component which does not participate in the power failure operation, and a third component which participates in the power failure operation, and the second component and the third component are steady-state power reduction components, the method comprises:
generating first power failure interrupt information for the first component and second power failure interrupt information for the second component and the third component when it is determined that a commercial power supply is stopped;
sending the first power failure interrupt information to the first component to control the first component to perform a first interrupt operation; wherein the first component comprises an uncoupled data hard disk belonging to the transient power reduction component;
sending the second power failure interrupt information to the second component to control the second component to perform a second interrupt operation; wherein the second component comprises a coupled data hard disk belonging to the steady-state power reduction components;
sending the second power failure interrupt information to the third component to control the third component to perform a third interrupt operation; wherein the third component comprises a memory device belonging to the steady-state power reduction components, and the first component, the second component and the third component are power reduction components of different levels, the first interrupt operation is an interrupt operation for the first component, the second interrupt operation is an interrupt operation for the second component, and the third interrupt operation is an interrupt operation for the third component.