US 12,292,783 B2
Adaptive wake-up for power conservation in a processor
Ping Zhou, San Diego, CA (US); Nikolai Schlegel, Danville, CA (US); Navid Ehsan, San Diego, CA (US); Zhimin Chen, San Jose, CA (US); and Gerard D. Jennings, Bavaria (DE)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 12, 2024, as Appl. No. 18/412,195.
Application 18/412,195 is a continuation of application No. 17/664,999, filed on May 25, 2022, granted, now 11,907,043.
Prior Publication US 2024/0241570 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3296 (2019.01); G06F 1/3209 (2019.01); G06F 1/3234 (2019.01); G06F 13/16 (2006.01)
CPC G06F 1/3296 (2013.01) [G06F 13/1668 (2013.01); G06F 1/3209 (2013.01); G06F 1/3243 (2013.01); G06F 1/3278 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of processing pipelines associated with different tasks, the plurality of processing pipelines including:
a first pipeline having first circuitry configured to process a wireless communication control channel;
a second pipeline having second circuitry configured to process a first wireless communication data channel; and
a third pipeline having third circuitry configured to process a second wireless communication data channel; and
a power management circuit configured to determine when to supply power to the first, second, and third circuitry wherein the power management circuit is configured to:
periodically power up the first circuitry to enable a listening operation to detect a data communication request via the wireless communication control channel;
power up the second and third circuitry when data communication is requested; and
transition the second and third circuitry to a lower power state in response to determining that data communication has ended.