US 12,292,780 B2
Computing system power management device, system and method
Nitin Chawla, Noida (IN); Anuj Grover, New Delhi (IN); Giuseppe Desoli, San Fermo Della Battaglia (IT); Kedar Janardan Dhori, Ghaziabad (IN); Thomas Boesch, Rovio (CH); and Promod Kumar, Greater Noida (IN)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed on Jun. 21, 2023, as Appl. No. 18/338,950.
Application 18/338,950 is a continuation of application No. 17/111,373, filed on Dec. 3, 2020, granted, now 11,726,543.
Claims priority of provisional application 62/947,815, filed on Dec. 13, 2019.
Prior Publication US 2023/0350483 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3287 (2019.01); G05F 3/24 (2006.01); G06F 1/3234 (2019.01); G06F 15/78 (2006.01); G11C 11/413 (2006.01)
CPC G06F 1/3275 (2013.01) [G05F 3/24 (2013.01); G06F 1/3287 (2013.01); G06F 15/7821 (2013.01); G11C 11/413 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A system on chip (SoC) device, comprising:
one or more processing cores; and
a memory coupled to the one or more processing cores, the memory including:
a plurality of memory circuits organized into a first set of memory circuits and a second set of memory circuits;
a common voltage regulator having an output coupled to respective gate driver nodes of the plurality of memory circuits, wherein the common voltage regulator, in operation, regulates a voltage provided to the plurality of memory circuits; and
memory control circuitry coupled to the plurality of memory circuits and the common voltage regulator, wherein the memory control circuitry, in operation:
controls transitions of memory circuits of the first set of memory circuits of the plurality of memory circuits between an active state and a retention state; and
maintains the second set of memory circuits of the plurality of memory circuits in the retention state, wherein,
the memory control circuitry comprises a set of active memory signal switches coupled to respective memory circuits of the first set of memory circuits,
a bias node of the second set of memory circuits is coupled to a bias node of the common voltage regulator, and
a bias node of a memory circuit of the first set of memory circuits is coupled to the bias node of the common voltage regulator via a first switch, and, in operation, the first switch is closed in response to opening of the respective active memory signal switch for the memory circuit of the first set of memory circuits.