US 12,292,777 B2
Management of a low-power mode
Gerald Baeza, Mulsanne (FR); Pascal Paillet, Le Mans (FR); and Loic Pallardy, Rouillon (FR)
Assigned to STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed by STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed on Nov. 2, 2021, as Appl. No. 17/517,382.
Claims priority of application No. 2011958 (FR), filed on Nov. 20, 2020.
Prior Publication US 2022/0164016 A1, May 26, 2022
Int. Cl. G06F 1/3206 (2019.01); G06F 1/324 (2019.01)
CPC G06F 1/324 (2013.01) [G06F 1/3206 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for managing a low-power mode of an electronic device comprising a processor, a first counter and a second counter, the method comprising:
driving, by a first oscillator, the first counter with a first clock;
driving, by a second oscillator, the second counter with a second clock, the second clock being faster than the first clock;
at a first request for transitioning the electronic device to the low-power mode:
storing values of the first and second counters on a first edge of the first clock;
stopping power to the second counter; and
deactivating the second oscillator; and
at a second request for transitioning the electronic device out of the low-power mode:
activating the second oscillator;
powering the second counter;
calculating a number of periods of the second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge; and
updating the value of the second counter with a calculated value.