US 12,292,755 B2
Fast power-up scheme for current mirrors
Saurabh Pandey, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 14, 2022, as Appl. No. 17/966,253.
Claims priority of application No. 202241036661 (IN), filed on Jun. 27, 2022.
Prior Publication US 2023/0418321 A1, Dec. 28, 2023
Int. Cl. G05F 3/26 (2006.01)
CPC G05F 3/262 (2013.01) 18 Claims
OG exemplary drawing
 
1. A power circuit comprising:
a sense transistor comprising a first source, a first gate, and a first drain;
a bias transistor comprising a second source, a second gate, and a second drain;
a discharge transistor comprising a third source, a third gate, and a third drain; and
an enable transistor comprising a fourth source and a fourth drain;
wherein:
the first gate is coupled to the second gate, the second drain, the third source, and the fourth drain;
the first drain is coupled to the third gate;
the third drain is coupled to a ground node; and
the first source, the second source, and the fourth source are coupled to a voltage supply node.