US 12,292,753 B2
Low power digital low-dropout power regulator
Baker Mohammad, Round Rock, TX (US); Dima Kilani, Abu Dhabi (AE); and Hani Saleh, Round Rock, TX (US)
Assigned to Khalifa University of Science and Technology, Abu Dhabi (AE)
Appl. No. 17/782,562
Filed by Khalifa University of Science and Technology, Abu Dhabi (AE)
PCT Filed Dec. 4, 2020, PCT No. PCT/US2020/063192
§ 371(c)(1), (2) Date Jun. 3, 2022,
PCT Pub. No. WO2021/113563, PCT Pub. Date Jun. 10, 2021.
Claims priority of provisional application 62/944,307, filed on Dec. 5, 2019.
Prior Publication US 2023/0012155 A1, Jan. 12, 2023
Int. Cl. G05F 1/59 (2006.01); G05F 1/46 (2006.01); G05F 1/575 (2006.01); H03K 19/094 (2006.01)
CPC G05F 1/59 (2013.01) [G05F 1/462 (2013.01); G05F 1/468 (2013.01); G05F 1/575 (2013.01); H03K 19/094 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A digital logic voltage regulator for generating a regulated output voltage, the digital logic voltage regulator comprising:
a voltage level comparator comprising a first input and a second input, wherein a target voltage is applied to the first input, wherein the regulated output voltage is applied to the second input, wherein the voltage level comparator generates a digital control signal that alternates between a first voltage level and a second voltage level in response to changes in relative voltage level between the regulated output voltage and the target voltage;
a power transistor comprising a power transistor gate terminal, a power transistor source terminal, and a power transistor drain terminal; wherein the digital control signal is applied to the power transistor gate terminal, wherein the power transistor source terminal is connected to a power source, and wherein the power transistor drain terminal is connected to an electrical load to supply electrical power having the regulated output voltage, wherein the digital control signal causes the power transistor to switch from off to on in response to a reduction of the regulated output voltage relative to the target voltage, and wherein the digital control signal causes the power transistor to switch from on to off in response to an increase of the regulated output voltage relative to the target voltage; and
a charge accumulator connected to the power transistor drain terminal so as to decrease variation in the regulated output voltage that would occur without the charge accumulator,
wherein:
the voltage level comparator comprises a logic circuit comprising the first input, the second input, and a logic circuit output;
the logic circuit generates a logic circuit output voltage that is output via the logic circuit output, wherein the logic circuit output voltage varies between a logic circuit upper limit output voltage and a logic circuit lower limit output voltage based on a relative difference between the regulated output voltage and the target voltage;
the logic circuit output voltage is equal to a logic circuit intermediate output voltage when the regulated output voltage is equal to the target voltage;
the logic circuit intermediate output voltage is less than the logic circuit upper limit output voltage and greater than the logic circuit lower limit output voltage;
the logic circuit output voltage is greater than the logic circuit intermediate output voltage when the regulated output voltage is less than the target voltage; and
the logic circuit output voltage is less than the logic circuit intermediate output voltage when the regulated output voltage is greater than the target voltage.