| CPC G05F 1/56 (2013.01) [H03K 17/22 (2013.01); H03K 19/17736 (2013.01)] | 20 Claims |

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1. An electronic system comprising:
first and second integrated circuit dies;
a third integrated circuit die comprising a first voltage regulator circuit, wherein a first supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a first supply voltage input of the first integrated circuit die, and wherein the first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage;
a fourth integrated circuit die comprising a second voltage regulator circuit that generates a second supply voltage, wherein a second supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a second supply voltage input of the second integrated circuit die, wherein the second voltage regulator circuit generates a second power ready signal that indicates when the second supply voltage has reached a second threshold voltage; and
a logic gate circuit comprising a first input coupled to receive the first power ready signal, a second input coupled to receive the second power ready signal, and an output that generates a third power ready signal based on the first and the second power ready signals; and
a fifth integrated circuit die comprising a power-on reset monitoring circuit, wherein the power-on reset monitoring circuit generates a power-on reset signal for the fifth integrated circuit die in response to a third supply voltage generated by a third voltage regulator circuit.
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