US 12,292,692 B2
Image stitching method for stitching product
Xiaobin Zhu, Shanghai (CN); Haichang Zheng, Shanghai (CN); Lijun Chen, Shanghai (CN); Xiaolong Wang, Shanghai (CN); and Yu Zhang, Shanghai (CN)
Assigned to Shanghai Huali Microelectronics Corporation, Shanghai (CN)
Filed by Shanghai Huali Microelectronics Corporation, Shanghai (CN)
Filed on Aug. 25, 2022, as Appl. No. 17/895,279.
Claims priority of application No. 202111409200.9 (CN), filed on Nov. 25, 2021.
Prior Publication US 2023/0161939 A1, May 25, 2023
Int. Cl. G03F 7/00 (2006.01); G03F 1/70 (2012.01); G06F 30/392 (2020.01); H10F 39/00 (2025.01)
CPC G03F 7/70475 (2013.01) [G03F 1/70 (2013.01); G06F 30/392 (2020.01); H10F 39/011 (2025.01)] 15 Claims
OG exemplary drawing
 
1. An image stitching method for a stitching product, comprising:
step 1: providing a chip design layout of the stitching product and dividing the chip design layout into unit regions and peripheral regions, each unit region being formed by repeatedly arranging a plurality of unit circuit images,
logic regions and cutting paths being provided in the peripheral regions, each logic region comprising a logic image, and each cutting path comprising a cutting path image,
adjacent chips of the stitching product being isolated by the cutting paths;
step 2: designing a mask layout according to the chip design layout, comprising:
step 21: setting unit mask images for defining the unit circuit images;
step 22: merging the logic images or cutting path images of adjacent areas between the unit regions together to set corresponding peripheral mask images;
step 23: comparing whether the peripheral mask images at symmetrical positions of the unit regions are the same, and merging same peripheral mask images into one; and
step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; and
step 3: performing repeated exposure to form the stitching product, comprising:
performing repeated exposure in the unit regions by adopting the unit mask images until all unit circuit images in the unit regions are defined on the chips; and
performing repeated exposure in the peripheral regions by adopting the corresponding peripheral mask images to form each logic image and each cutting path image on the chips, exposed adjacent areas being not exposed any longer in a subsequent exposure process of the chip after each logic image and each cutting path image in the adjacent areas are defined on one of the chips in the adjacent areas between the unit regions of the adjacent chips.