US 12,292,663 B2
Liquid crystal display panel
Gen Koide, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Sep. 6, 2023, as Appl. No. 18/242,660.
Application 18/242,660 is a continuation of application No. 17/841,971, filed on Jun. 16, 2022, granted, now 11,754,897.
Application 17/841,971 is a continuation of application No. 17/201,554, filed on Mar. 15, 2021, granted, now 11,372,296, issued on Jun. 28, 2022.
Application 17/201,554 is a continuation of application No. 16/810,322, filed on Mar. 5, 2020, granted, now 10,948,793, issued on Mar. 16, 2021.
Application 16/810,322 is a continuation of application No. 16/122,408, filed on Sep. 5, 2018, granted, now 10,591,793, issued on Mar. 17, 2020.
Application 16/122,408 is a continuation of application No. 15/144,178, filed on May 2, 2016, granted, now 10,095,078, issued on Oct. 9, 2018.
Application 15/144,178 is a continuation of application No. 14/157,053, filed on Jan. 16, 2014, granted, now 9,348,190, issued on May 24, 2016.
Claims priority of application No. 2013-008822 (JP), filed on Jan. 21, 2013.
Prior Publication US 2023/0408878 A1, Dec. 21, 2023
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/136 (2006.01); G02F 1/1368 (2006.01); H10D 30/67 (2025.01)
CPC G02F 1/136286 (2013.01) [G02F 1/133514 (2013.01); G02F 1/134336 (2013.01); G02F 1/1368 (2013.01); G02F 1/13606 (2021.01); G02F 2201/40 (2013.01); H10D 30/6733 (2025.01); H10D 30/6757 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A liquid crystal display panel comprising:
a first substrate;
a second substrate disposed so as to face the first substrate with a liquid crystal layer interposed therebetween;
a pixel electrode;
a thin-film transistor including a semiconductor layer and coupled to the pixel electrode;
a scan line extending overall in a first direction;
a signal line crossing the scan line; and
an insulation layer that insulates the scan line and the signal line,
wherein the scan line comprises:
a main scan line including first scan line portions extending in a first direction and second scan line portions extending in a second direction different from the first direction; and
a bypass portion coupled to respective second scan line portions, the bypass portion extending in the first direction and deviated in the second direction from an intersection where a first scan line portion and a second scan line portion cross each other,
wherein the thin-film transistor includes a first channel and a second channel,
the second channel is disposed where the semiconductor layer crosses the bypass portion,
the first scan line portions are disposed apart from the bypass portion in the second direction, and
each of the first scan line portions crosses a corresponding one of a plurality of the signal lines.