US 12,292,472 B2
Testing a single chip in a wafer probing system
Thomas Gentner, Boeblingen (DE); Alejandro Alberto Cook Lobo, Renningen (DE); and Otto Andreas Torreiter, Leinfelden-Echterdingen (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 29, 2023, as Appl. No. 18/477,578.
Application 18/477,578 is a continuation of application No. 17/643,216, filed on Dec. 8, 2021, granted, now 11,808,808.
Prior Publication US 2024/0019488 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2893 (2013.01) [G01R 31/2891 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method for testing at least one single chip in a wafer probing system, at least comprising:
providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface;
loading the adapter plate with the at least one single chip into the wafer probing system;
moving the vacuum chuck together with the adapter plate to a predefined search area for probes of the wafer probing system;
determining an exact position of the at least one single chip in the adapter plate in the search area, wherein a neural network is used in a determination phase of a positioning algorithm for determining a translational and rotational matrix defining adjusting positions of the vacuum chuck;
adjusting the position of the vacuum chuck until a front surface of the at least one single chip is in an operational region for being contacted by the probes of the wafer probing system;
adding the adjusted position of the vacuum chuck corresponding to the at least one single chip positioned in the operational region to identification data of the loaded adapter plate, wherein the identification data comprises an origin point of a top left position of a cutout on the adapter plate;
contacting the at least one single chip electrically with probes of the wafer probing system; and
testing the at least one single chip with test routines stored in a controller of the wafer probing system.