US 12,292,471 B2
Test method
Kenichi Ishii, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Jul. 13, 2022, as Appl. No. 17/864,351.
Claims priority of application No. 2021-142744 (JP), filed on Sep. 1, 2021.
Prior Publication US 2023/0063471 A1, Mar. 2, 2023
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2887 (2013.01) 20 Claims
OG exemplary drawing
 
1. A test method of a semiconductor apparatus, the semiconductor apparatus comprising a pad, the test method comprising:
bringing one or more probe pins into contact with the pad;
testing the semiconductor apparatus in a first test step with the one or more probe pins in contact with the pad with each of the one or more probe pins contacting the pad at a corresponding first contact position;
bringing the one or more probe pins into contact with the pad of the semiconductor apparatus in a shifted state where each of the one or more probe pins are in contact with the pad at a corresponding second contact position that is displaced by a distance from the corresponding first contact position; and
testing the semiconductor apparatus in a second test step with the one or more probe pins in the shifted state,
wherein in the first test step, a corresponding first test area having a center and a predefined size is set for each of the one or more probe pins, with the center of the corresponding first test area being located at the corresponding first contact position for each of the one or more probe pins, so as to allow the semiconductor apparatus can be screened for the presence of a defective point beneath the pad and covered by the corresponding first test area with each of the one or more probe pins located at the corresponding first contact position thereof, and
wherein in the second test step, a corresponding second test area having a center and a predefined size is set for each of the one or more probe pins, with the center of the corresponding second test area being located at the corresponding second contact position for each of the one or more probe pins, so as to allow the semiconductor apparatus can be screened for the presence of a defective point beneath the pad and covered by the corresponding second test area, and not covered by the corresponding first test area, with each of the one or more probe pins located at the corresponding second contact position thereof.