US 12,292,455 B2
Chip socket, testing fixture and chip testing method thereof
Shih-Ting Lin, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Feb. 23, 2024, as Appl. No. 18/585,507.
Application 18/585,507 is a division of application No. 17/468,014, filed on Sep. 7, 2021, granted, now 11,959,939.
Prior Publication US 2024/0192252 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 1/04 (2006.01); G01R 31/28 (2006.01); G11C 29/56 (2006.01); H01L 23/00 (2006.01); H01L 23/32 (2006.01); H01L 23/498 (2006.01); H01R 12/70 (2011.01)
CPC G01R 1/0466 (2013.01) [G01R 31/2886 (2013.01); G11C 29/56 (2013.01); H01L 23/32 (2013.01); H01L 23/49827 (2013.01); H01L 24/67 (2013.01); H01R 12/7076 (2013.01); H01L 24/14 (2013.01); H01L 2224/1412 (2013.01); H01L 2224/67 (2013.01); H01L 2924/1436 (2013.01); H01R 2201/20 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A testing fixture, comprising:
a first circuit board;
a chip socket mounted on the first circuit board, and the chip socket comprising:
a pedestal having a first surface and a second surface;
a plurality of conductive traces formed in the pedestal;
a plurality of clamp structures disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures being coupled to a corresponding conductive trace of the plurality of conductive traces, wherein the clamp structure has a gap configured to be deformed its size for clamping a solder ball of a chip to be tested in the gap so as to allow the solder ball of the chip for being inserted into and pulled from the gap, wherein the plurality of clamp structures are conductive, wherein the gap has an opening with a first width and a bottom with a second width, wherein when the solder ball of the chip is not inserted into the gap, the first width of the opening of the gap is equal to the second width of the bottom of the gap, wherein when the solder ball of the chip is inserted into the gap, the first width of the opening of the gap is increased and is greater than the second width of the bottom of the gap; and
a plurality of electrical contacts disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts being coupled to a corresponding clamp structure of the plurality of clamp structures through a corresponding conductive trace of the plurality of conductive traces; and
a second circuit board comprising a slot, wherein the first circuit board is attached to the slot as an inline memory module; and the chip to be tested is coupled to the second circuit board through the first circuit board.