US 12,291,104 B1
System for mutual inductance cancellation for T-type multilevel converters
Yilun Luo, Ann Arbor, MI (US); Junghoon Kim, Springboro, OH (US); Khorshed Mohammed Alam, Canton, MI (US); Chandra S. Namuduri, Troy, MI (US); and Rashmi Prasad, Troy, MI (US)
Assigned to GM Global Technology Operations LLC, Detroit, MI (US)
Filed by GM GLOBAL TECHNOLOGY OPERATIONS LLC, Detroit, MI (US)
Filed on Nov. 3, 2023, as Appl. No. 18/501,340.
Int. Cl. H02M 7/42 (2006.01); B60L 15/00 (2006.01); H02M 1/088 (2006.01); H02M 1/12 (2006.01); H02M 7/483 (2007.01)
CPC B60L 15/007 (2013.01) [H02M 1/088 (2013.01); H02M 1/12 (2013.01); H02M 7/483 (2013.01); B60L 2210/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-phase power inverter for an electric drivetrain, the multi-phase power inverter comprising:
a plurality of T-type multilevel power converters arranged between a high-voltage DC power supply and an electric machine, wherein each of the plurality of T-type multilevel power converters is a solid-state integrated circuit (IC) including:
a positive DC power bus;
a negative DC power bus;
a neutral bus;
a plurality of semiconductor switches disposed in a stacked arrangement, wherein the plurality of semiconductor switches is interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches including:
a first semiconductor switch connected to a first node;
a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus;
a third semiconductor switch connected to the first node;
a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and
an AC bus connected to the first node, wherein the AC bus is connected to the electric machine;
a first heat sink adjoined to at least one of the positive DC power bus and/or the negative DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and
a second heat sink adjoined to the neutral bus of the solid-state IC via a second DBC substrate.