US 12,290,900 B2
Methods for thinning substrates for semiconductor devices
Krishna Chetry, Richardson, TX (US); and Ganesan Radhakrishnan, Richardson, TX (US)
Assigned to Qorvo US, Inc., Greensboro, NC (US)
Appl. No. 18/577,590
Filed by Qorvo US, Inc., Greensboro, NC (US)
PCT Filed Mar. 27, 2023, PCT No. PCT/US2023/016353
§ 371(c)(1), (2) Date Jan. 8, 2024,
PCT Pub. No. WO2023/234998, PCT Pub. Date Dec. 7, 2023.
Claims priority of provisional application 63/347,340, filed on May 31, 2022.
Prior Publication US 2024/0173813 A1, May 30, 2024
Int. Cl. B24B 7/22 (2006.01); B24B 37/00 (2012.01); B24B 37/005 (2012.01); B24B 37/04 (2012.01); B24B 41/06 (2012.01); H01L 21/306 (2006.01)
CPC B24B 7/228 (2013.01) [B24B 37/00 (2013.01); B24B 37/005 (2013.01); B24B 37/042 (2013.01); B24B 41/06 (2013.01); H01L 21/30625 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for thinning a device wafer, the method comprising:
performing a first grinding process to thin the device wafer from a first thickness to a second thickness, wherein the performance of the first grinding process comprises:
monitoring a first total thickness variation (TTV) of the device wafer during the performance of the first grinding process; and
adjusting at least one first grinding parameter during the performance of the first grinding process based on the monitored first TTV of the device wafer, wherein the first grinding process comprises a rough or coarse grinding process;
performing a second grinding process to thin the device wafer from the second thickness to a third thickness, wherein the performance of the second grinding process comprises:
monitoring a second TTV of the device wafer during the performance of the second grinding process; and
adjusting at least one second grinding parameter during the performance of the second grinding process based on the monitored second TTV of the device wafer, wherein the second grinding process comprises a fine grinding process; and
performing a chemical mechanical polish (CMP) process to thin the device wafer from the third thickness to a fourth thickness, wherein at least one polishing parameter associated with the CMP process is adjusted during the performance of the CMP process based on a thickness profile for the device wafer.