US RE49,954 E1
Fabrication of nano-sheet transistors with different threshold voltages
Karthik Balakrishnan, White Plains, NY (US); Kangguo Cheng, Schenectady, NY (US); Pouya Hashemi, White Plains, NY (US); and Alexander Reznicek, Troy, NY (US)
Assigned to TESSERA LLC, San Jose, CA (US)
Filed by TESSERA LLC, San Jose, CA (US)
Filed on Jun. 3, 2021, as Appl. No. 17/338,459.
Application 17/338,459 is a continuation of application No. 15/268,993, filed on Sep. 19, 2016, granted, now 9,653,289, issued on Apr. 26, 2017.
Application 17/338,459 is a reissue of application No. 15/462,372, filed on Mar. 17, 2017, granted, now 10,312,337, issued on Jun. 4, 2019.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/336 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 27/088 (2013.01); H01L 21/02603 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/4983 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/775 (2013.01); H01L 29/78651 (2013.01); H01L 29/78696 (2013.01)] 41 Claims
OG exemplary drawing
 
[ 20. A method of forming nano-sheet devices, the method comprising:
providing at least two dummy gate structures, each of the dummy gate structures (i) disposed on a cut-stack comprising alternating sacrificial release layers and nano-sheet channel layers and (ii) comprising opposing side spacers, each side spacer having opposing inside and outside surfaces;
forming first lateral indentations of a first depth in a first plurality of sacrificial release layers of a first cut-stack;
forming second lateral indentations of a second depth in a second plurality of sacrificial release layers of a second cut-stack, wherein the second depth is greater than the first depth; and
filling the first lateral indentations in the first cut-stack and the second lateral indentations in the second cut-stack with a dielectric material. ]