CPC H10K 59/1213 (2023.02) [G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); H10K 59/131 (2023.02); G09G 2300/0465 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01)] | 20 Claims |
1. A driving backplane, comprising:
a base substrate;
a plurality of data lines, and a first gate line and a second gate line that are adjacent, all of which are disposed on the base substrate; and
a plurality of pixel driving circuits disposed on the base substrate, each pixel driving circuit including a first transistor, the first transistor including an active layer, the active layer including an active portion, a first conductive portion and a second conductive portion;
active layers of first transistors in the plurality of pixel driving circuits further including first contact portions; the plurality of pixel driving circuits including a first pixel driving circuit coupled to a data line of the plurality of data lines and the first gate line, and a second pixel driving circuit coupled to the data line of the plurality of data lines and the second gate line,
wherein a first conductive portion of a first transistor included in the first pixel driving circuit and a first conductive portion of a first transistor included in the second pixel driving circuit are in contact through a first contact portion of the first contact portions, and are coupled to the data line of the plurality of data lines through the first contact portion.
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