US 11,974,421 B2
SRAM layout for double patterning
James Walter Blatchford, Richardson, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 15, 2020, as Appl. No. 17/071,724.
Application 14/867,676 is a division of application No. 13/622,971, filed on Sep. 19, 2012, granted, now 10,181,474, issued on Jan. 15, 2019.
Application 17/071,724 is a continuation of application No. 16/211,753, filed on Dec. 6, 2018, granted, now 10,840,250.
Application 16/211,753 is a continuation of application No. 14/867,676, filed on Sep. 28, 2015, granted, now 10,103,153, issued on Oct. 16, 2018.
Claims priority of provisional application 61/536,346, filed on Sep. 19, 2011.
Prior Publication US 2021/0028179 A1, Jan. 28, 2021
Int. Cl. H10B 10/00 (2023.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 27/02 (2006.01)
CPC H10B 10/12 (2023.02) [H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/0207 (2013.01); H10B 10/125 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit having an SRAM, comprising:
forming a gate layer having a first gate structure with a long dimension extending in a first direction, the long dimension being a width or a length from a top down view of the SRAM;
forming a contact layer having a first contact with a first portion with a long dimension extending in the first direction, the long dimension being a width or a length from the top down view and a second portion with a long dimension extending in a second direction at a diagonal from the first direction, the long dimension being a width or a length from the top down view;
forming a power (Vdd) routing in a metal-1 layer, a portion of the power routing extending over the first gate structure and having a long dimension that extends in a third direction at a diagonal from the first direction, the long dimension being a width or a length from the top down view, wherein the portion of the power routing is defined with a first metal-1 mask and the metal-1 layer includes one or more portions defined with a second metal-1 mask different than the first metal-1 mask; and
a first bit line routing and a second bit line routing in a metal-2 layer.