CPC H04N 23/741 (2023.01) [G06T 3/40 (2013.01); G06T 7/194 (2017.01); G06T 7/60 (2013.01); H04N 23/11 (2023.01); H04N 23/51 (2023.01); H04N 23/56 (2023.01); H04N 23/71 (2023.01); H04N 23/74 (2023.01); H04N 23/957 (2023.01); H04N 25/75 (2023.01); H04N 25/767 (2023.01); H04N 25/772 (2023.01); H01L 27/14681 (2013.01)] | 26 Claims |
1. A computational pixel imaging system comprising a computational pixel imager having a plurality of pixels, each pixel including:
a detector;
a detector biasing line arranged to apply a bias or supply voltage modulated at a first frequency to the detector;
one or more counters arranged to digitize a signal output from the detector; and
a mixer, wherein an output from the mixer is used to determine a periodicity of count-up and count-down cycles for one or more of the counters.
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