CPC H01L 29/7786 (2013.01) [H01L 27/0605 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/404 (2013.01); H03K 17/6871 (2013.01)] | 21 Claims |
1. A method of operating a circuit comprising a depletion-mode transistor having a channel and an enhancement-mode transistor wherein a source of the depletion-mode transistor is connected to a drain of the enhancement-mode transistor, the method comprising:
biasing a gate of the depletion-mode transistor and a gate of the enhancement-mode transistor at zero volts and biasing a positive voltage to a drain of the depletion-mode transistor and blocking a current in a forward direction;
changing the bias of the gate of the enhancement-mode transistor to a first voltage greater than a threshold voltage of the enhancement-mode transistor while the gate of the depletion-mode transistor remains biased at zero volts such that a first current is allowed to flow through the channel in a forward direction; and
changing the bias of the gate of the depletion-mode transistor to a second voltage while the gate of the enhancement-mode transistor remains biased at the first voltage such that a second current is allowed to flow through the channel in a forward direction; wherein the second current is greater than the first current.
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