US 11,973,121 B2
Device contacts in integrated circuit structures
Guillaume Bouche, Portland, OR (US); Andy Chih-Hung Wei, Yamhill, OR (US); Mwilwa Tambwe, Beaverton, OR (US); Sean T. Ma, Portland, OR (US); and Piyush Mohan Sinha, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2020, as Appl. No. 16/832,283.
Prior Publication US 2021/0305380 A1, Sep. 30, 2021
Int. Cl. H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/41733 (2013.01) [H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first source/drain (S/D) contact over a first S/D region of a transistor device;
a gate contact, wherein the gate contact is in contact with a gate and with the first S/D contact; and
a second S/D contact over a second S/D region of the transistor device, the second S/D region and the first S/D region on opposite sides of the gate, wherein a height of the second S/D contact is less than a height of the first S/D contact.