US 11,973,090 B2
System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects
Laurent Blanquart, Westlake Village, CA (US)
Assigned to DePuy Synthes Products, Inc., Raynham, MA (US)
Filed by DePuy Synthes Products, Inc., Raynham, MA (US)
Filed on Sep. 6, 2022, as Appl. No. 17/930,043.
Application 17/930,043 is a continuation of application No. 17/088,502, filed on Nov. 3, 2020, granted, now 11,432,715, issued on Sep. 6, 2022.
Application 17/088,502 is a continuation of application No. 16/886,587, filed on May 28, 2020, granted, now 10,863,894, issued on Dec. 15, 2020.
Application 16/886,587 is a continuation of application No. 15/489,588, filed on Apr. 17, 2017, granted, now 10,709,319, issued on Jul. 14, 2020.
Application 15/489,588 is a continuation of application No. 13/471,432, filed on May 14, 2012, granted, now 9,622,650, issued on Apr. 18, 2017.
Claims priority of provisional application 61/485,432, filed on May 12, 2011.
Claims priority of provisional application 61/485,440, filed on May 12, 2011.
Claims priority of provisional application 61/485,426, filed on May 12, 2011.
Claims priority of provisional application 61/485,435, filed on May 12, 2011.
Prior Publication US 2022/0409033 A1, Dec. 29, 2022
Int. Cl. H01L 27/146 (2006.01); A61B 1/00 (2006.01); A61B 1/05 (2006.01); A61B 1/06 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 27/12 (2006.01); H04N 23/56 (2023.01); H04N 25/75 (2023.01); H04N 25/767 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01); H01L 31/028 (2006.01); H01L 31/0296 (2006.01); H01L 31/0304 (2006.01); H04N 23/50 (2023.01)
CPC H01L 27/14603 (2013.01) [A61B 1/00009 (2013.01); A61B 1/051 (2013.01); A61B 1/0676 (2013.01); H01L 24/17 (2013.01); H01L 24/20 (2013.01); H01L 24/28 (2013.01); H01L 25/0657 (2013.01); H01L 27/124 (2013.01); H01L 27/146 (2013.01); H01L 27/14601 (2013.01); H01L 27/14609 (2013.01); H01L 27/14618 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14638 (2013.01); H01L 27/1464 (2013.01); H01L 27/14641 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H01L 27/1469 (2013.01); H04N 23/56 (2023.01); H04N 25/75 (2023.01); H04N 25/767 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01); H01L 31/028 (2013.01); H01L 31/0296 (2013.01); H01L 31/0304 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/381 (2013.01); H04N 23/555 (2023.01)] 20 Claims
OG exemplary drawing
 
1. An imaging sensor comprising:
a pixel array comprising a plurality of pixels formed into a plurality of pixel columns, wherein the plurality of pixel columns are divided into a plurality of pixel sub-columns;
a plurality of pixel sub-column buses that correspond with the plurality of pixel sub-columns, such that at least one of the plurality of pixel sub-column buses is associated with one of the plurality of pixel sub-columns such that each of the plurality of pixel sub-columns are configured to be read independently;
a plurality of supporting circuits configured to process data received from the plurality of pixels, wherein the plurality of supporting circuits are formed into a plurality of supporting circuit columns, and wherein the plurality of supporting circuit columns are divided into a plurality of supporting circuit sub-columns;
a plurality of supporting circuit sub-column buses that correspond with the plurality of supporting circuit sub-columns, such that at least one of the plurality of supporting circuit sub-column buses is associated with one of the plurality of supporting circuit sub-columns;
wherein at least a portion of the plurality of supporting circuit sub-column buses and at least a portion of the plurality of pixel sub-columns buses are superimposed; and
a plurality of interconnects, wherein at least one interconnect electrically connects each of the plurality of pixel sub-column buses to each of the plurality of supporting circuit sub-column buses such that each of the plurality of supporting circuit sub-columns receives pixel data from a corresponding pixel sub-column;
wherein the plurality of interconnects are positioned anywhere along an intercept of the plurality of pixel sub-column buses and the plurality of circuit sub-column buses, wherein the intercept is defined by the superimposition of the at least a portion of the plurality of pixel sub-column buses directly with the at least a portion of the plurality of the circuit sub-column buses.