US 11,973,084 B2
Array substrate, manufacturing method thereof, and display device thereof
Dan Bai, Hubei (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN); and WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Wuhan (CN)
Appl. No. 17/293,792
Filed by WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN); and WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Hubei (CN)
PCT Filed Apr. 22, 2021, PCT No. PCT/CN2021/088843
§ 371(c)(1), (2) Date May 13, 2021,
PCT Pub. No. WO2022/217635, PCT Pub. Date Oct. 20, 2022.
Prior Publication US 2022/0328534 A1, Oct. 13, 2022
Int. Cl. H01L 27/12 (2006.01)
CPC H01L 27/1237 (2013.01) [H01L 27/127 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate;
a plurality of first thin film transistors disposed on the substrate, the first thin film transistors comprising a first gate electrode layer and a second gate electrode layer, and the second gate electrode layer disposed on a side of the first gate electrode layer away from the substrate;
a plurality of second thin film transistors disposed on the substrate, the second thin film transistors comprising a third gate electrode layer; and
a gate electrode insulation layer disposed between the first gate electrode layer and the second gate electrode layer and on a surface of a side of the third gate electrode layer near the substrate, the gate electrode insulation layer being silicon nitride material;
wherein the first thin film transistors further comprise:
a first active layer disposed on the substrate, a first insulation layer covering the first active layer;
the first gate electrode layer disposed on a surface of a side of the first insulation layer away from the substrate;
the gate electrode insulation layer disposed on a surface of a side of the first gate electrode layer away from the first insulation layer;
the second gate electrode layer disposed on a surface of a side of the first gate electrode layer away from the gate electrode insulation layer;
a first dielectric layer disposed on the surface of the side of the first insulation layer away from the substrate and covering the first gate electrode layer, the gate electrode insulation layer, and the second gate electrode layer; and
a first source and drain electrode disposed on a surface of a side of a second dielectric layer away from the second insulation layer, and connected to the first active layer;
wherein the second thin film transistors further comprise:
a metal layer disposed on the substrate, and disposed on a same layer as the first active layer;
the third gate electrode layer disposed on the gate electrode insulation layer;
a second active layer disposed on a surface of a side of the first dielectric layer away from the first insulation layer, a second insulation layer covering the second active layer;
a fourth gate electrode layer disposed on a surface of a side of a second insulation layer away from the first dielectric layer, a second dielectric layer covering the fourth gate electrode layer; and
a second source and drain electrode disposed on a surface of a side of a second dielectric layer away from the second insulation layer ,and connected to the second active layer and the metal layer.