US 11,973,057 B2
Through-silicon transmission lines and other structures enabled by same
Ed Balboni, Littleton, MA (US); Ozan Gurbuz, Portland, OR (US); William B. Beckwith, Palmer Lake, CO (US); and Paul Harlan Rekemeyer, Cambridge, MA (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/548,050.
Claims priority of provisional application 63/125,450, filed on Dec. 15, 2020.
Prior Publication US 2022/0189917 A1, Jun. 16, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16146 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly comprising:
an assembly support structure;
a first die including a first side and a second side, the first die further including:
a pair of hot through-substrate-vias (TSVs) extending through the first die between the first and second sides of the first die, the pair of hot TSVs arranged as twin radio frequency signal transmission lines in a differential configuration;
a plurality of ground vias extending through the first die between the first and second sides of the first die, wherein the plurality of ground vias are disposed around the pair of hot TSVs; and
at least one signal interconnect structure electrically connected to at least one hot TSV of the pair of hot TSVs, the at least one signal interconnect structure disposed on the second side of the first die; and
a second die between the assembly support structure and the first die, the second die including a first side and a second side, the second die further including at least one signal interconnect structure disposed on the first side of the second die;
wherein the first die is connected to the second die via a signal die-to-die (DTD) interconnect structure comprising the at least one signal interconnect structure of the first die and the at least one signal interconnect structure of the second die.