US 11,973,016 B2
Semiconductor device
Elvir Kahrimanovic, Villach (AT); Gerhard Noebauer, Villach (AT); Oliver Blank, Villach (AT); and Alessandro Ferrara, Villach (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Appl. No. 17/620,472
Filed by Infineon Technologies Austria AG, Villach (AT)
PCT Filed Apr. 29, 2020, PCT No. PCT/EP2020/061972
§ 371(c)(1), (2) Date Dec. 17, 2021,
PCT Pub. No. WO2021/001084, PCT Pub. Date Jan. 7, 2021.
Claims priority of application No. 19184547 (EP), filed on Jul. 4, 2019.
Prior Publication US 2022/0254703 A1, Aug. 11, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 29/417 (2006.01); H01L 29/43 (2006.01)
CPC H01L 23/49844 (2013.01) [H01L 23/49513 (2013.01); H01L 23/49562 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 29/41741 (2013.01); H01L 29/435 (2013.01); H01L 23/4952 (2013.01); H01L 23/49524 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/29116 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/73221 (2013.01); H01L 2224/73263 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/0544 (2013.01); H01L 2924/13091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface;
a first metallization structure on the first surface and comprising at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode, and at least one gate pad coupled to the gate electrode;
a second metallization structure on the second surface and comprising a conductive layer and an electrically insulating inorganic layer and forming an outermost surface of the semiconductor device,
wherein the outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating inorganic layer,
wherein the semiconductor die comprises a doped drain region forming the drain electrode,
wherein the electrically insulating inorganic layer is arranged directly on the second surface of the semiconductor die,
wherein the conductive layer comprises a metallic connection layer arranged directly on the electrically insulating inorganic layer.