US 11,972,987 B2
Die level product modeling without die level input data
Richard Burch, McKinney, TX (US); Qing Zhu, Rowlett, TX (US); and Jonathan Holt, Sachse, TX (US)
Assigned to PDF Solutions, Inc., Santa Clara, CA (US)
Filed by PDF Solutions, Inc., Santa Clara, CA (US)
Filed on Oct. 16, 2020, as Appl. No. 17/072,817.
Claims priority of provisional application 62/916,163, filed on Oct. 16, 2019.
Prior Publication US 2021/0118754 A1, Apr. 22, 2021
Int. Cl. H01L 21/66 (2006.01); G06N 20/00 (2019.01)
CPC H01L 22/20 (2013.01) [G06N 20/00 (2019.01); H01L 22/14 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method, comprising:
obtaining testing data from each of a respective plurality of test sites formed and distributed across a semiconductor wafer, prior to slicing a multiplicity of dies from the wafer;
obtaining a die level map of the semiconductor wafer that includes graphical details regarding a multiplicity of semiconductor features and corresponding locations for each feature on the semiconductor wafer; and
for each of the multiplicity of dies on the semiconductor wafer:
providing the testing data and the die level map as input data to a multiplicity of neural networks, each neural network corresponding to a respective one of the multiplicity of dies and each neural network programmed with instructions to (i) determine non-linear relationships among the input data for the respective die, (ii) impute from the determined non-linear relationship among the input data a plurality of input process parameters relevant to the respective die, and (iii) predict yield for the respective die from the imputed input process parameters, wherein each neural network is initially configured from training sets of input data.