US 11,972,986 B2
Process for producing semiconductor wafers
Michael Boy, Waging am See (DE); and Christina Kruegler, Dietersburg (DE)
Assigned to Siltronic AG, Munich (DE)
Appl. No. 16/981,048
Filed by SILTRONIC AG, Munich (DE)
PCT Filed Mar. 13, 2019, PCT No. PCT/EP2019/056220
§ 371(c)(1), (2) Date Sep. 15, 2020,
PCT Pub. No. WO2019/175207, PCT Pub. Date Sep. 19, 2019.
Claims priority of application No. 10 2018 203 945.3 (DE), filed on Mar. 15, 2018.
Prior Publication US 2021/0111080 A1, Apr. 15, 2021
Int. Cl. C30B 33/08 (2006.01); G01N 21/21 (2006.01); G01N 21/95 (2006.01); H01L 21/324 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01)
CPC H01L 22/20 (2013.01) [C30B 33/08 (2013.01); G01N 21/21 (2013.01); G01N 21/9505 (2013.01); H01L 21/324 (2013.01); H01L 21/67288 (2013.01)] 17 Claims
 
1. A process for producing semiconductor wafers comprising the following steps in the given sequence:
a) pulling a single-crystal rod of a semiconductor material from a melt and optionally cylindrically grinding the rod,
b) separating a plurality of semiconductor wafers from the rod;
c) removing at least one wafer for analysis from the single-crystal rod,
d) performing a first thermal treatment step corresponding to a thermal budget to which the wafer is subjected during fabrication of semiconductor devices on the wafer, and performing a second thermal treatment step with the at least one wafer of semiconductor material, wherein in the second thermal treatment step a radial temperature gradient acts on at least one side of the semiconductor wafer from the inside outward or from the outside inward,
e) analyzing the wafer of semiconductor material treated in step d) with respect to the possible formation and/or the extent of stress fields,
f) distinguishing this wafer and further wafers of the plurality of semiconductor wafers separated from a rod section represented by this wafer into stress-optimized wafers conforming to the thermal budget to which the wafers are subjected during the fabrication of semiconductor devices on the wafer from rejected wafers not conforming to this thermal budget.