US 11,972,970 B1
Singulation process for chiplets
Florian G. Herrault, Malibu, CA (US); and Joel Wong, Malibu, CA (US)
Assigned to HRL LABORATORIES, LLC, Malibu, CA (US)
Filed by HRL Laboratories, LLC, Malibu, CA (US)
Filed on Jun. 28, 2021, as Appl. No. 17/361,186.
Claims priority of provisional application 63/073,344, filed on Sep. 1, 2020.
Int. Cl. H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 21/82 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 21/6836 (2013.01) [H01L 21/76802 (2013.01); H01L 21/8213 (2013.01); H01L 21/8234 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of forming a two-dimensional array of components singulated from a wafer and temporarily adhered as a two-dimensional array on a stretchable tape, the method comprising: forming the two-dimensional array of components on and/or in the wafer with streets between neighboring transistors in said two-dimensional array; temporarily adhering an exposed portion of each component on and/or in the wafer face down on a carrier substrate using a temporary adhesive; etching, thru the wafer, apertures aligning with the streets between neighboring components to singulate the components; adhering a stretchable tape to the backsides of the two-dimensional array of components; and dissolving the adhesive thereby releasing the two-dimensional array of singulated components adhered to the stretchable tape from the carrier substrate.