US 11,972,834 B2
Low power and robust level-shifting pulse latch for dual-power memories
Adithya Bhaskaran, Austin, TX (US); Rahul Sahu, Bangalore (IN); and Sharad Kumar Gupta, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Appl. No. 17/774,138
Filed by Qualcomm Incorporated, San Diego, CA (US)
PCT Filed Nov. 9, 2020, PCT No. PCT/US2020/059708
§ 371(c)(1), (2) Date May 3, 2022,
PCT Pub. No. WO2021/096809, PCT Pub. Date May 20, 2021.
Claims priority of application No. 201941045726 (IN), filed on Nov. 11, 2019.
Prior Publication US 2022/0293148 A1, Sep. 15, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/1087 (2013.01) [G11C 7/1012 (2013.01); G11C 7/1084 (2013.01); G11C 7/222 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A level-shifting pulse latch, comprising:
a level-shifting inverter configured to invert and level-shift a system clock signal from a system power domain powered by a system power supply voltage into a memory-power-domain inverted clock signal for a memory power domain powered by a memory power supply voltage;
a pass transistor configured to switch on to pass the memory-power-domain inverted clock signal to form a latch input signal on an input signal node responsive to an assertion of both a memory select signal and the system clock signal; and
a memory-power-domain latch configured to latch the latch input signal to provide a self-timed memory clock signal for a memory.