US 11,972,269 B2
Device enhancements for software defined silicon implementations
Katalin Klara Bartfai-Walcott, El Dorado Hills, CA (US); Arkadiusz Berent, Tuchom (PL); Vasuki Chilukuri, Hillsboro, OR (US); Mark Baldwin, Hillsboro, OR (US); Vasudevan Srinivasan, Portland, OR (US); and Bartosz Gotowalski, Gdansk (PL)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 30, 2022, as Appl. No. 18/092,163.
Application 18/092,163 is a continuation of application No. 17/033,267, filed on Sep. 25, 2020, granted, now 11,599,368.
Claims priority of provisional application 63/049,017, filed on Jul. 7, 2020.
Claims priority of provisional application 62/937,032, filed on Nov. 18, 2019.
Claims priority of provisional application 62/907,353, filed on Sep. 27, 2019.
Prior Publication US 2023/0132432 A1, May 4, 2023
Int. Cl. G06F 9/445 (2018.01); G06F 11/30 (2006.01); G06F 21/10 (2013.01); G06Q 10/087 (2023.01); G06Q 30/04 (2012.01); H04L 9/32 (2006.01)
CPC G06F 9/44505 (2013.01) [G06F 11/3058 (2013.01); G06F 21/105 (2013.01); H04L 9/3247 (2013.01); H04L 9/3268 (2013.01); H04L 9/3278 (2013.01); G06F 21/1075 (2023.08); G06Q 10/087 (2013.01); G06Q 30/04 (2013.01)] 25 Claims
OG exemplary drawing
 
15. A system comprising:
at least one memory;
machine readable instructions; and
processor circuitry to at least one of instantiate or execute the machine readable instructions to:
associate a first stock keeping unit with a processor platform including a plurality of processor cores, respective ones of the processor cores configurable to be active or dormant, the first stock keeping unit associated with a first number of processor cores of the processor platform configured to be active, remaining ones of the processor cores to be dormant processor cores;
command the processor platform to activate one or more of the dormant processor cores to cause the processor platform to provide a second number of processor cores configured to be active; and
generate a second stock keeping unit for the processor platform, the second stock keeping unit associated with the processor platform having the second number of processor cores configured to be active.