| CPC G06F 9/3806 (2013.01) [G06F 9/325 (2013.01)] | 17 Claims |
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1. An apparatus comprising:
processing circuitry to perform processing operations in response to micro-operations;
front end circuitry to supply the micro-operations to be processed by the processing circuitry; and
prediction circuitry to generate a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of the loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry; in which:
the front end circuitry is configured to vary, based on a level of confidence in the prediction of the number of the loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry;
the prediction circuitry is configured to generate the prediction of the number of the loop iterations in response to detecting program flow reaching, or being predicted to reach, an address predicted as corresponding to a loop-terminating branch instruction for controlling, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a loop body or process a following instruction to be processed after a final iteration of the loop body; and
the loop body comprises operations to:
determine a variable number of bytes to be processed in a current iteration;
perform at least one processing operation based on the variable number of bytes determined for the current iteration, the at least one processing operation including at least one of a load operation and a store operation; and
update, based on the variable number of bytes, a remaining bytes parameter indicative of a remaining number of bytes to be processed.
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