US 11,972,144 B2
Dynamic status registers array
Giuseppe Cariello, Boise, ID (US); and Reshmi Basu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 11, 2021, as Appl. No. 17/399,889.
Prior Publication US 2023/0046313 A1, Feb. 16, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory dice;
a data bus coupled with each of the plurality of memory dice; and
a controller coupled with each of the plurality of memory dice via the data bus, the controller configured to:
transmit a first command associated with a first operation to a first memory die of the plurality of memory dice, wherein the first command comprises an assignment of the first operation to a queue slot of a status bank;
transmit a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a status associated with the status bank;
transmit a third command associated with a second operation to a second memory die of the plurality of memory dice subsequent to transmitting the first command, wherein the third command comprises a second assignment of the second operation to a second queue slot of the status bank; and
receive, via a first channel of the data bus determined based at least in part on the assigned queue slot of the status bank, the status of the first operation based at least in part on transmitting the second command to the first memory die.