US 11,972,132 B2
Data processing engine arrangement in a device
Juan J. Noguera Serra, San Jose, CA (US); Goran H K Bilski, Molndal (SE); Jan Langer, Chemnitz (DE); Baris Ozgul, Dublin (IE); Richard L. Walke, Edinburgh (GB); Ralph D. Wittig, Menlo Park, CA (US); Kornelis A. Vissers, Sunnyvale, CA (US); Tim Tuan, San Jose, CA (US); and David Clarke, Dublin (IE)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Dec. 22, 2022, as Appl. No. 18/145,810.
Application 17/097,917 is a division of application No. 15/944,160, filed on Apr. 3, 2018, granted, now 10,866,753, issued on Dec. 15, 2020.
Application 18/145,810 is a continuation of application No. 17/097,917, filed on Nov. 13, 2020, granted, now 11,573,726.
Prior Publication US 2023/0131698 A1, Apr. 27, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01)
CPC G06F 3/0647 (2013.01) [G06F 3/061 (2013.01); G06F 3/0683 (2013.01); G06F 13/1663 (2013.01); G06F 15/17331 (2013.01); G06F 15/7807 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device, comprising:
a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns;
wherein each data processing engine includes a core, a memory module including a memory, and a direct memory access engine;
wherein each data processing engine includes a stream switch, wherein the stream switch of each data processing engine is connected to the core and the direct memory access engine in a same data processing engine, and to the stream switch of one or more adjacent data processing engines;
wherein each memory module includes a plurality of memory interfaces including a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines; and
wherein each core coupled to a selected memory interface of the plurality of memory interfaces of a selected memory module is configured to access the memory of the selected memory module via the selected memory interface independently of the stream switch.