US 11,971,620 B2
Display panel and electronic device
Yang Hu, Beijing (CN); Yuanhui Guo, Beijing (CN); Xia Shi, Beijing (CN); and Yujie Gao, Beijing (CN)
Assigned to WUHAN BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Hubei (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/907,986
Filed by WUHAN BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Hubei (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Nov. 22, 2021, PCT No. PCT/CN2021/131962
§ 371(c)(1), (2) Date Aug. 30, 2022,
PCT Pub. No. WO2022/151836, PCT Pub. Date Jul. 21, 2022.
Claims priority of application No. 202110041652.X (CN), filed on Jan. 13, 2021.
Prior Publication US 2023/0116568 A1, Apr. 13, 2023
Int. Cl. G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/133377 (2013.01) [G02F 1/134354 (2021.01); G02F 1/136286 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A display panel, comprising an array substrate and an opposing substrate which forms a cell with the array substrate:
wherein:
the array substrate comprises a first substrate, scan lines, data lines, a first blocking wall and a second blocking wall, and the scan lines, the data lines, the first blocking wall and the second blocking wall are formed on a side of the first substrate close to the opposing substrate;
the data lines extend in a first direction, the scan lines extend in a second direction, and the first direction intersects with the second direction;
the first blocking wall and the second blocking wall are respectively arranged on opposite sides of at least one of the scan lines in the first direction, and each of the first blocking wall and the second blocking wall comprises a first blocking layer arranged in a same layer as the scan lines and arranged apart from the scan lines and a second blocking layer arranged in a same layer as the data lines and arranged apart from the data lines, and an orthographic projection of the second blocking layer on the first substrate overlaps with an orthographic projection of the first blocking layer on the first substrate;
a distance between the first blocking layer and a corresponding one of the scan lines in the first direction is a first distance, a distance between the second blocking layer and the corresponding one of scan lines in the first direction is a second distance, and the second distance is greater than the first distance;
wherein:
the opposing substrate comprises a second substrate and a spacer on a side of the second substrate close to the array substrate, a surface of the spacer close to the first substrate is a top surface, and an orthographic projection of the top surface of the spacer on the first substrate is within an orthographic projection of the corresponding one of the scan lines on the first substrate and between orthographic projections of the first blocking wall and the second blocking wall on the first substrate; and
a size of the top surface of the spacer in the first direction is greater than the first distance;
wherein the orthographic projection of the second blocking layer on the first substrate is within the orthographic projection of the first blocking layer on the first substrate, and the first direction is perpendicular to the second direction;
wherein the array substrate further comprises first common lines formed on the first substrate and extending in the second direction, and the first common lines and the scan lines are arranged in a same layer and arranged apart from each other;
wherein the first blocking layer of the second blocking wall is a partial structure of a corresponding one of the first common lines;
wherein the array substrate further comprises a plurality of sub-pixel units, which are arranged as an array on the first substrate along the second direction and the first direction;
wherein each of the sub-pixel units comprises a pixel electrode, a common electrode and a transistor, wherein:
the transistor comprises a gate electrode, a first electrode and a second electrode, the gate electrode is connected to one of the scan lines, the first electrode is connected to the pixel electrode, and the second electrode is connected to one of the data lines;
wherein an orthographic projection of the common electrode on the first substrate overlaps with an orthographic projection of the pixel electrode on the first substrate, and the common electrode is connected to one of the first common lines;
wherein the pixel electrode is arranged on a side of the common electrode away from the first substrate, and the pixel electrode comprises:
a first electrode portion comprising a first connection bar extending in a first direction and a plurality of first electrode bars arranged at intervals in the first direction, wherein the first connection bar has a first side and a second side which are opposite in the second direction, the plurality of first electrode bars are arranged on the first side of the first connection bar and connected to the first connection bar, and ends of adjacent first electrode bars away from the first connection bar are in an open shape;
a second electrode portion arranged apart from the first electrode portion in the first direction, wherein the second electrode portion comprises a second connection bar extending in the first direction and a plurality of second electrode bars arranged at intervals in the first direction, the second connection bar is located at a position on the first side away from the second side, the second connection bar has a third side and a fourth side which are opposite in the second direction, the third side is located at a position on the fourth side close to the first side, the plurality of second electrode bars are arranged on the third side of the second connection bar and connected to the second connection bar, and ends of adjacent second electrode bars away from the second connection bar are in an open shape; and
a conductive connection portion arranged between the first electrode portion and the second electrode portion, wherein both ends of the conductive connection portion are connected to the first connection bar and the second connection bar, respectively, and an area of the conductive connection portion is larger than an area of each of the first electrode bars and an area of each of the second electrode bars;
wherein the conductive connection portion comprises:
a first conductive connection bar and a second conductive connection bar that are arranged apart in the second direction and both extend in the first direction; and
at least two third conductive connection bars located between the first conductive connection bar and the second conductive connection bar and arranged apart in the first direction, wherein two ends of each of the third conductive connection bars are connected to the first conductive connection bar and the second conductive connection bar, respectively;
wherein the first conductive connection bar is connected to the first connection bar, and the second conductive connection bar is connected to the second connection bar.