CPC A61B 6/4233 (2013.01) [A61B 6/502 (2013.01); G09G 3/20 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0297 (2013.01)] | 20 Claims |
1. A flat panel detector, divided into a detection region and a peripheral region surrounding the detection region, and comprising:
a plurality of scanning signal lines, located in the detection region and divided into a plurality of groups; and
at least one stage of first demultiplexer, located in a portion of the peripheral region on one side of the detection region, wherein signal output terminals of a first stage of first demultiplexer are connected with the scanning signal lines in one-to-one correspondence, signal output terminals of another stage of first demultiplexer serves as signal input terminals of the previous stage of first demultiplexer, a current stage of first demultiplexer is configured to provide signals of the signal input terminals of the current stage of first demultiplexer to the signal output terminals of the current stage of first demultiplexer in time division, and a quantity of the signal input terminals and a quantity of the signal output terminals are reduced stage by stage from the first stage of first demultiplexer to the last stage of first demultiplexer.
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