US 12,290,005 B2
Magnetoresistive random access memory
Hui-Lin Wang, Taipei (TW); Yu-Ping Wang, Hsinchu (TW); Chen-Yi Weng, New Taipei (TW); Chin-Yang Hsieh, Tainan (TW); Si-Han Tsai, Taichung (TW); Che-Wei Chang, Taichung (TW); and Jing-Yin Jhang, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on May 30, 2024, as Appl. No. 18/679,437.
Application 18/679,437 is a continuation of application No. 18/202,275, filed on May 25, 2023, granted, now 12,029,139.
Application 18/202,275 is a continuation of application No. 17/463,541, filed on Aug. 31, 2021, granted, now 11,706,996, issued on Jul. 18, 2023.
Application 17/463,541 is a continuation of application No. 16/589,083, filed on Sep. 30, 2019, granted, now 11,139,428, issued on Oct. 5, 2021.
Claims priority of application No. 201910827096.1 (CN), filed on Sep. 3, 2019.
Prior Publication US 2024/0324472 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/85 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/85 (2023.02); H10N 50/01 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region;
a first MTJ on the MTJ region;
a first metal interconnection on the logic region;
a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection; and
a passivation layer around the first MTJ and the second MTJ, wherein the passivation layer between the first MTJ and the second MTJ comprises a V-shape.