| CPC H10N 50/80 (2023.02) [H01L 27/0248 (2013.01); H10B 61/22 (2023.02)] | 6 Claims |

|
1. A semiconductor device, comprising:
a substrate having an array region defined thereon;
magnetic tunneling junction (MTJ) patterns on the array region, wherein the MTJ patterns are arranged in an array;
a ring of dummy pattern surrounding the array region, wherein the ring of dummy pattern comprises:
a ring of MTJ pattern surrounding the array region, wherein the ring of MTJ pattern is made of a single MTJ; and
a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
|