US 12,290,003 B2
Conductive structure connection with interconnect structure
Sheng-Chau Chen, Tainan (TW); Cheng-Tai Hsiao, Tainan (TW); Cheng-Yuan Tsai, Chu-Pei (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/079,043.
Application 18/079,043 is a continuation of application No. 17/528,574, filed on Nov. 17, 2021, granted, now 12,185,640.
Application 17/528,574 is a continuation of application No. 16/732,385, filed on Jan. 2, 2020, granted, now 11,183,627, issued on Nov. 23, 2021.
Application 16/732,385 is a continuation of application No. 16/051,759, filed on Aug. 1, 2018, granted, now 10,529,913, issued on Jan. 7, 2020.
Claims priority of provisional application 62/691,244, filed on Jun. 28, 2018.
Prior Publication US 2023/0103309 A1, Apr. 6, 2023
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a conductive structure over a semiconductor substrate;
a first dielectric layer over the conductive structure;
a second dielectric layer over the first dielectric layer;
an interconnect structure over the conductive structure and disposed in the first and second dielectric layers, wherein the interconnect structure has a protrusion in contact with a sidewall of the conductive structure, wherein the interconnect structure comprises an interconnect liner surrounding a conductive interconnect body, wherein a bottom surface of the protrusion is flat and below a top surface of the conductive structure; and
a sidewall spacer disposed on the sidewall of the conductive structure.