US 12,289,979 B2
Deposition system for high accuracy patterning
Ping-Yin Liu, Yonghe (TW); Chia-Shiung Tsai, Hsin-Chu (TW); Xin-Hua Huang, Xihu Township (TW); Yu-Hsing Chang, Taipei (TW); and Yeong-Jyh Lin, Caotun Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,008.
Application 18/361,008 is a division of application No. 16/806,064, filed on Mar. 2, 2020, granted, now 11,818,944.
Prior Publication US 2023/0371354 A1, Nov. 16, 2023
Int. Cl. H10K 71/16 (2023.01); C23C 16/04 (2006.01); C23C 16/458 (2006.01); H10K 50/125 (2023.01); H10K 71/00 (2023.01)
CPC H10K 71/166 (2023.02) [C23C 16/042 (2013.01); C23C 16/4584 (2013.01); H10K 50/125 (2023.02); H10K 71/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A processing tool comprising:
a first wafer-mounting frame configured to retain a target wafer;
a second wafer-mounting frame configured to retain a masking wafer, the first and second wafer-mounting frames configured to be clamped together; and
an imaging device arranged between the first wafer-mounting frame and the second wafer-mounting frame, the imaging device configured to measure an amount of misalignment between the target wafer and the masking wafer when the target wafer is retained by the first wafer-mounting frame and the masking wafer is retained by the second wafer-mounting frame.