US 12,289,975 B2
Display device
Tae Jin Kong, Yongin-si (KR); Hyun Min Cho, Yongin-si (KR); Dae Hyun Kim, Yongin-si (KR); Su Mi Moon, Yongin-si (KR); Xinxing Li, Yongin-si (KR); and Hee Keun Lee, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Appl. No. 17/624,673
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
PCT Filed Jun. 26, 2020, PCT No. PCT/KR2020/008410
§ 371(c)(1), (2) Date Jan. 4, 2022,
PCT Pub. No. WO2021/006509, PCT Pub. Date Jan. 14, 2021.
Claims priority of application No. 10-2019-0081533 (KR), filed on Jul. 5, 2019.
Prior Publication US 2022/0278173 A1, Sep. 1, 2022
Int. Cl. H01L 27/32 (2006.01); H10K 50/854 (2023.01); H10K 59/122 (2023.01); H10K 59/35 (2023.01); H10K 59/38 (2023.01); H10K 102/10 (2023.01)
CPC H10K 59/38 (2023.02) [H10K 50/854 (2023.02); H10K 59/122 (2023.02); H10K 59/351 (2023.02); H10K 2102/102 (2023.02); H10K 2102/103 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
a first sub-pixel including a first light emitting element disposed on and directly above a main surface of the substrate and in a first sub-pixel area of the substrate;
a second sub-pixel including a second light emitting element disposed in a second sub-pixel area located in a first direction with respect to the first sub-pixel area of the substrate;
a bank layer disposed between the first sub-pixel and the second sub-pixel;
a first color filter pattern disposed on the first sub-pixel and the bank layer; and
a second color filter pattern disposed on the second sub-pixel and the bank layer, wherein
the first light emitting element emits light having a first color,
the second light emitting element emits light having a second color different from the first color,
the first color filter pattern and the second color filter pattern at least partially overlap each other on the bank layer, and
each of the first light emitting element and the second light emitting element includes a first semiconductor layer and a second semiconductor layer, both of the first and second semiconductor layers intersecting a plane parallel to a plane defined by the main surface of the substrate.