US 12,289,957 B2
Display panel and manufacturing method thereof
Macai Lu, Shenzhen (CN)
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/419,729
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed May 27, 2021, PCT No. PCT/CN2021/096445
§ 371(c)(1), (2) Date Jun. 30, 2021,
PCT Pub. No. WO2022/227167, PCT Pub. Date Nov. 3, 2022.
Claims priority of application No. 202110458047.2 (CN), filed on Apr. 27, 2021.
Prior Publication US 2023/0139990 A1, May 4, 2023
Int. Cl. H10K 59/121 (2023.01); H01L 27/12 (2006.01); H10K 59/12 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/1213 (2023.02) [H10K 71/00 (2023.02); H01L 27/1229 (2013.01); H01L 27/1248 (2013.01); H10K 59/1201 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A display panel, comprising a plurality of gate lines and data lines arranged crosswise and insulated from each other to form a plurality of sub-pixels arranged in an array, wherein each of the sub-pixels is at least provided with a first thin film transistor, a second thin film transistor, a pixel capacitor, a power supply terminal, and a light-emitting unit;
wherein the first thin film transistor comprises a low temperature polysilicon thin film transistor, the low temperature polysilicon thin film transistor comprises a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode is connected to the pixel capacitor, and the first source electrode is connected to the power supply terminal, and the first drain electrode is connected to the light-emitting unit;
the second thin film transistor comprises an oxide thin film transistor, the oxide thin film transistor comprises a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode is connected to the gate lines, the second source electrode is connected to the data lines, and the second drain electrode is connected to the first gate electrode; and
the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed in a same layer, and the first source electrode and the first drain electrode are insulated from the second source electrode and the second drain electrode;
wherein the display panel further comprises a substrate, the low temperature polysilicon thin film transistor comprises a first active layer disposed on the substrate, the first gate electrode is disposed on one side of the first active layer, the first source electrode and the first drain electrode are disposed on one side of the first active layer away from the substrate, and the first source electrode and the first drain electrode are connected to the first active layer;
the oxide thin film transistor comprises a second active layer disposed on the substrate, the second gate electrode is disposed on one side of the second active layer away from the substrate, the second source electrode and the second drain electrode are disposed under the second active layer, and the second gate electrode is disposed on the side of the second active layer away from the second source electrode;
wherein the display panel further comprises:
a first gate insulating layer disposed on the side of the first active layer away from the substrate;
a first gate electrode layer disposed on one side of the first gate insulating layer away from the first active layer, wherein the first gate electrode layer comprises the first gate electrode;
an interlayer insulating layer disposed on one side of the first gate electrode layer away from the first gate insulating layer;
a source and drain electrode layer disposed on one side of the interlayer insulating layer away from the first gate electrode layer;
a first passivation layer disposed on one side of the source and drain electrode layer away from the interlayer insulating layer;
the second active layer disposed on one side of the first passivation layer away from the source and drain electrode layer;
a second gate insulating layer disposed on one side of the second active layer away from the first passivation layer;
a second gate electrode layer disposed on one side of the second gate insulating layer away from the second active layer, wherein the second gate electrode layer comprises the second gate electrode and the gate lines; and
a second passivation layer disposed on one side of the second gate electrode layer away from the second gate insulating layer;
wherein the source and drain electrode layer comprises the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and the data lines;
wherein the first passivation layer is disposed on the first source electrode and the first drain electrode and extends above the second source electrode and the second drain electrode.