US 12,289,924 B2
Transistors having increased effective channel width
Chiao-Ti Huang, Santa Clara, CA (US); Sing-Chung Hu, Santa Clara, CA (US); Yuanwei Zheng, Santa Clara, CA (US); and Bill Phan, Santa Clara, CA (US)
Assigned to OmniVision Technologies, Inc., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Mar. 2, 2023, as Appl. No. 18/177,494.
Application 18/177,494 is a division of application No. 16/830,086, filed on Mar. 25, 2020, granted, now 11,616,088.
Prior Publication US 2023/0207587 A1, Jun. 29, 2023
Int. Cl. H10F 39/18 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/27 (2025.01); H10F 39/00 (2025.01)
CPC H10F 39/80377 (2025.01) [H01L 21/76224 (2013.01); H10D 30/024 (2025.01); H10D 30/6217 (2025.01); H10D 64/513 (2025.01); H10D 64/516 (2025.01); H10D 64/518 (2025.01); H10F 39/18 (2025.01); H10F 39/802 (2025.01); H10F 39/80373 (2025.01); H10F 39/807 (2025.01); H10D 30/6211 (2025.01); H10F 39/813 (2025.01)] 15 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a floating diffusion disposed in the semiconductor substrate;
a transfer transistor configured for coupling the photodiode to the floating diffusion, the transfer transistor comprising a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate; and
a transistor coupled to the floating diffusion, the transistor comprising:
a planar gate disposed proximate to the first surface of the semiconductor substrate; and
a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction, wherein the plurality of vertical gate electrodes are configured along a channel width direction of the transistor
wherein the plurality of vertical gate electrodes comprise:
a first vertical gate electrode extending a second depth into the semiconductor substrate;
a second vertical gate electrode extending the second depth into the semiconductor substrate; and
a third vertical gate electrode extending a third depth into the semiconductor substrate, wherein the third vertical gate electrode is configured between the first vertical gate electrode and the second vertical gate electrode;
wherein the second depth is less than the third depth, and wherein the third depth is
the same as the first depth of the vertical transfer gate.