US 12,289,920 B2
Semiconductor device and method for manufacturing the same
Qiyue Zhao, Suzhou (CN); and Yu Shi, Suzhou (CN)
Assigned to INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD., Suzhou (CN)
Appl. No. 17/442,141
Filed by INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD., Suzhou (CN)
PCT Filed Aug. 11, 2021, PCT No. PCT/CN2021/112109
§ 371(c)(1), (2) Date Sep. 23, 2021,
PCT Pub. No. WO2022/174562, PCT Pub. Date Aug. 25, 2022.
Claims priority of application No. PCT/CN2021/076958 (WO), filed on Feb. 19, 2021.
Prior Publication US 2023/0095367 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/82 (2025.01); H10D 84/05 (2025.01)
CPC H10D 84/82 (2025.01) [H10D 84/05 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first nitride-based semiconductor layer disposed above a substrate;
a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
a first electrode and a second S/D electrode disposed above the second nitride-based semiconductor layer;
a first gate electrode and a second gate electrode disposed above the second nitride-based semiconductor layer and between the first and second electrodes;
a first passivation layer disposed on the second nitride-based semiconductor layer and covering the first and second gate electrodes;
a first field plate disposed over the first gate electrode and over the first passivation layer and having a first end portion directly above the first gate electrode, wherein the first passivation layer has a first portion covered with the first end portion of the first field plate and a second portion free from coverage of the first field plate;
a second passivation layer disposed on the first passivation layer and covering the first field plate; and
a conductive layer disposed over the second passivation layer and extending from the first field plate to the second gate electrode and making contact with a portion of the second nitride-based semiconductor layer, wherein the second passivation layer has a first portion covered by the conductive layer and a second portion free from coverage of the conductive layer, wherein a thickness difference between the first and second portions of the first passivation layer is less than a thickness difference between the first and second portions of the second passivation layer.