| CPC H10D 84/206 (2025.01) [H01L 23/481 (2013.01); H10D 1/474 (2025.01); H10D 1/711 (2025.01)] | 20 Claims |

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1. A semiconductor device comprising:
a dielectric layer over a back end of line (BEOL) metal layer;
a metallic resistive layer over the dielectric layer;
a resistor comprising a metallic resistive film that is a first portion of the metallic resistive layer; and
a metal-insulator-metal (MIM) capacitor comprising a top plate, a bottom plate, and an insulator between the top plate and the bottom plate, wherein the insulator of the MIM capacitor comprises at least two layers including a first layer that is a second portion of the metallic resistive layer and a second layer that is the dielectric layer, and wherein the metallic resistive layer comprises a metallic dielectric film.
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