| CPC H10D 64/111 (2025.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 30/0281 (2025.01); H10D 30/658 (2025.01); H10D 62/115 (2025.01)] | 19 Claims |
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1. A structure comprising:
a gate structure over a semiconductor substrate;
a drift region under the gate structure;
a source region adjacent to the gate structure;
a drain region in the drift region;
an isolation structure within the drift region;
an insulator layer lining the isolation structure;
interlevel dielectric material over the insulator layer; and
a contact extending from the source region and into the isolation structure within the drift region,
wherein the contact comprises a first via interconnect structure electrically connecting to the source region, a metal field plate extension electrically connecting to the first via interconnect structure and extending partly over the drift region, and a second via interconnect structure electrically connecting to the metal field plate extension, wherein the second via interconnect structure extends into the isolation structure below the insulator layer.
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